Investigations on Implementation of Ternary Content Addressable Memory Architecture in Spartan 3e Fpga
نویسندگان
چکیده
1Mtech scholar, Department of ECE, GECI, Kerala, India 2Associate Professor, Department of ECE, GECI, Kerala, India ---------------------------------------------------------------------***--------------------------------------------------------------------Abstract – The Field Programmable Gate Array (FPGA) implementation of Ternary Content Addressable Memory (TCAM) is a demanding area of research to address the requirements of data base querying systems and high speed networking. Major investigation area in the Content Addressable Memory (CAM) architecture design is the performance metrics such as area, power and latency in the context of miniaturization, high speed and low power requirements of electronic gadget market. Z-TCAM is one of the latest popular architectures available in FPGA based TCAM. This paper is an investigation on implementation of Z-TCAM architecture in a low cost FPGA platform. The chosen hardware implementation platform is Digilent Basys2 board which works well with all versions of Xilinx Integrated Synthesis Environment (ISE) tool and free Web Pack. The architecture under study is implemented in SPARTAN 3E FPGA to obtain hardware utilization of 12.26%, latency of 3110.55 nS and power consumption of 45.16 mW.
منابع مشابه
FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations
Ternary Content Addressable memory is a type of memory that allows the memory to be searched by content rather than by address. It performs high speed lookup operations within a single clock cycle. But when compared to RAM technology the conventional TCAM circuitry has certain limitations such as low access time, low storage capacity, circuit complexity and high cost. So we can use the benefits...
متن کاملFPGA Implementation of a 64-Bit RISC Processor Using VHDL
In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-inself test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on th...
متن کاملImplementation of LPM Address Generators on FPGAs
We propose the multiple LUT cascade as a means to configure an ninput LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our design on a Xilinx Spartan-3 FPGA for n = 32 and k = 504 ∼ 511. Also, we compare our design to a Xi...
متن کاملFPGA Implementation of 3/6 SRFFT Algorithm for Length 6*m DFTS
The Fast Fourier Transform (FFT) requires high Computational power, ability to choose the algorithm and architecture to implement it. This project explains the realization of a 3/6 FFT processor based on a pipeline architecture. The implementation has been made on a Field Programmable Gate Array (FPGA) as a way of obtaining high performance at economical price and a short time of realization. F...
متن کاملEfficient Implementation of Adaptive Noise Canceller Using FPGA for Automobile Applications
This paper presents the architecture and implementation of a real time adaptive NLMS filter for nonstationary noise cancellation in a car environment.The active noise control techniques using adaptive digital filters are very much suitable and well proven.The proposed efficient Adaptive Noise Canceller is realized using Xilinx System Generator 12.3 on Spartan 3E FPGA. System Generator is a DSP ...
متن کامل